For the past several decades, the shrinking of feature sizes in integrated circuits has enabled faster and more efficient devices. Scaling to smaller feature sizes also enables increased densities of functional units on the limited real estate of semiconductor chips. As the geometries of electronic devices continue to shrink and the density of devices continues to increase, the size and aspect ratio of the features are becoming more aggressive, e.g., feature sizes of 15 nm or smaller and aspect ratios of 10 or greater are being considered. The increasingly smaller devices are not without issue, and new device fabrication techniques are necessary to overcome the physical obstacles that become apparent at small sizes.
Currently, the semiconductor industry relies on the ability to reduce or scale the dimensions of the basic components, including the gate dielectric, of its transistor devices to obtain lower power consumption and higher performance. To reduce transistor size, the thickness of the gate dielectric is reduced in proportion to the shrinkage of the gate length. Increased scaling and other requirements in microelectronic devices have created the need to use other dielectric materials as gate dielectrics, in particular dielectrics with higher dielectric constants (k) to replace the conventional use of various combinations of SiO2, Si3N4, and SiON. Practical higher dielectric constant (k) materials, in some cases, have the properties of high permittivity, thermal stability, high film and surface quality and smoothness, low hysteresis characteristics, low leakage current density, and long term reliability. However, polysilicon gates and high-k dielectric materials have interface issues.
Therefore, there is a need for a process to form dielectric materials, especially high-k dielectric materials, which have reduced defects from oxide formation.